FIG. 1 shows a conventional phase-locked loop (PLL) circuit. The conventional PLL circuit comprises a phase detector (PD) 3, a charge pump (CP) 4, an external loop filter (LF) 5, a voltage-controlled oscillator (VCO) 1 and a frequency divider (DIV) 2. The phase detector 3 detects the phase difference between the reference frequency fRef and the actual frequency first dependent on the VCO. If the phase of the actual frequency fist leads the phase of the reference frequency fRef, a falling pulse DW, the duration of which corresponds to the phase difference between the reference frequency fRef and the actual frequency first, is generated and directed to a DW output 15 of the phase detector 3. If the phase of the actual frequency fist lags the phase of the reference frequency fRef, a rising pulse UP, the duration of which corresponds to the phase difference between the reference frequency fRef and the actual frequency fist, is generated and directed to a UP output 14 of the phase detector 3. If the actual frequency fist synchronizes with the reference frequency fRef, a UP pulse as well as a DW pulse are directed simultaneously to the UP and DW outputs 14, 15 respectively.
Upon receipt of the UP pulse from the phase detector 3, the charge pump 4 charges the external loop filter 5. Upon receipt of the DW pulse from the phase detector 3, the charge pump 4 discharges the external loop filter 5. If the applied voltage V1 of the loop filter 5 increases upon receipt of a high voltage from the charge pump 4, the frequency fvco in the VCO 1 also rises. If, on the other hand, the applied voltage V1 in the external loop filter 5 decreases as a result of receipt of the lower voltage from the charge pump 4, the oscillation frequency fvco the VCO 1 drops. The loop filter 5 and the charge pump 4 form components of the final control element 36 for the VCO 1. The final control element 36 converts the measurement result from the chase detector into a voltage, with which the oscillation frequency of the VCO can be influenced.
If the actual frequency fist dependent on the oscillation frequency fvco of the VCO 1 is lower than the reference frequency fRef and the phase of the actual frequency lags the phase of the reference frequency fRef, UP pulses are generated in the phase detector 3, as a result of which the charge pump 4 increases the voltage V1 at the external loop filer 5. As a result of the increase in the voltage V1 the oscillation frequency fvco of the VCO 1 rises. The increase in the oscillation frequency fvco causes the increase in the actual frequency fist at the phase detector 3 and thus the approximation to the reference frequency fRef.
If, however, the actual frequency fist dependent on the oscillation frequency fvco of the VCO 1 is higher than the reference frequency fRef, i.e. if the phase of the actual frequency fist leads the phase of the reference frequency fRef, a DW pulse DW is generated in the phase detector 3, as a result of which the charge pump 4 decreases the voltage V1 at the external loop filter 5. As a result of the decrease in the voltage V1 the oscillation frequency fvco the VCO 1 also decreases. The decrease in the oscillation frequency fvco causes the drop in the actual frequency fist at the phase detector 3 and thus the approximation to the reference frequency fRef.
To smooth the current pulses of the charge pump 4, which are initiated because of the UP and DW pulses in the phase detector 3, a filter capacitor CG 8 is located between the charge pump 4 and the loop filter 5.
By virtue of the fact that the sensitivity and thus the transconductance Kvco=f(V1) of the VCO 1 is not constant over the whole voltage range, but can vary by a factor 4 over the whole voltage range, for example, an additional switch 17 is located between the input of the VCO 1 and the charge pump 4, which should at least partially compensate this effect.
The external loop filter 5 comprises a first capacitor CS1 9, with which the voltage V1 for the VCO 1 is generated, and an array connected in series comprising a resistor RS 28 with a second capacitor CS2 10 connected in parallel.
The dimensioning of such a PLL circuit for applications in the field of telecommunications is configured such that circuit-related disturbances are as small as possible. Firstly, disturbances are caused by the currents I1 and I2. However, this disturbance influence decreases in relation to the useful signal V1, the greater the current I from the charge pump 4. This, in turn, necessitates an increase in the capacitance of the capacitor CS1 9 in order to come to the identical voltage value V1.
Secondly, a further disturbance is caused by the modulation of the output frequency with the thermal noise of the resistor RS 28 in the VCO 1. This disturbance increases, the greater the resistance RS 28 and the greater the transconductance Kvco of the VCO. Typical values for a loop filter 5 in the field of telecommunications are I=0.1 mA−2 mA; CS1+CSs2=200 pF−5 nF; RS=100 Ω−2 kΩ.
However, a disadvantage here is that, because of the large capacitances required as a result of the reduction of disturbance influences, the loop filter 5 cannot be integrated into the PLL circuit because, for example, even in the case of a typically used capacitance of CS1 of 1 nF, for example, a surface area of approximately 1 mm2 is required. If the capacitances CS1 and CS2 were of smaller dimensions in the loop filter 5, then the current I would also have to be decreased and the resistance RS increased. As a result, the disturbances arising in the PLL circuit would be too great and therefore the requirements above all for the field of telecommunications could not be met.